A Space Between Spaces

InSemi is constantly on a look out of people who understand the potential of innovation and who can think in-between the physical and the digital spaces. If you are someone who has a passion for VLSI, Embedded design and electronics, we have all the space for you.

Do write to us with your resume using below form..
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Current Openings

Experience: 8+Yrs

Location: Bangalore

As a Staff Firmware Development Engineer, you will join a team of professionals in developing software and real-time firmware solutions for state-of-art System-on-Chip (SoC) storage devices with embedded MIPS processors. Reporting to the Manager of Firmware Development, your responsibilities will include, but are not limited to the following:

  • Participate as a member of the team in the technical analysis and integration of storage software involving SATA/SAS/NVMe RAID controller technologies
  • Program MIPS processors using C and assembly language to implement core software/firmware components as well as device drivers.
  • Work directly with customers in the development of their software solutions using Microsemi devices and software/firmware components
  • Work in collaboration with other Microsemi sites to design solutions and resolve customer issues
  • Participate in detailed design and code reviews of implementations by team
  • Sustain current product and guide next generation product to production.
  • Troubleshoot and resolve complex software problems in embedded real-time systems.
  • Analyze software performance (d-cache and i-cache hit/miss rates, cycle counts, etc.) of firmware.
  • Write comprehensive engineering documentation.
  • Present technical information to teams of engineers and technical marketing personnel.

Experience: 6-9Yrs

Location: Bangalore

Desired Skills:

MS, M Tech, BE Computer Science, Computer Engineering/Electronics Engineering with 6 – 9 years of experience

  • Has a very good understanding is well versed with CPU (X86/ARM) and SOC architecture
  • Has a good understanding of system BIOS and UEFI.
  • Thorough understanding of OS internals, preferably on Linux
  • Should have good knowledge of C/C++ programming
  • Should have good knowledge of Linux Kernel porting
  • Hands-on kernel development and device driver
  • Should have good knowledge of source control management system (GIT/Perforce/SVN)
  • Understand software design, architecture, implementation of use cases and test cases, and enable customers in application of this software into their differentiated innovative products
  • Strong verbal and written communication skills, and interpersonal / teamwork skills.

Good to have

  • Understanding of PC BIOS internals including APICs, SuperIO, SATA storage devices, USB controllers.
  • Understanding system Busses (PCI, PCIe, etc)

Location: Bangalore

Parasitic Extraction CAD Contractor

Looking for a qualified individual who can provide user support for Analog/Mixed Signal Post-Layout extraction tool flows. This position will be hands-on, heavily involved in design day-to-day issues and in addition, interact with EDA vendors, PDK development, and process technology teams to provide timely solutions to improve productivity. Responsibilities also include CAD tool techfile evaluations (debugging and proper qualification of all RCX techfile related issues), test, and documentation.

Requirements include:

  • B.S in Electrical Engineering or Computer Science + 3  years of Parasitic Extraction  EDA support experience
  • Expertise in the following CAD Tools: IC6, and IC12/18 Cadence Quantus, Voltus-Fi, APS EMIR, Virtuoso ADE-L/XL, Spectre, and Synopsys StarRC, Quickcap
  • Solid background in programming skills, circuit design, and device physics knowledge to help solve circuit design and post-layout extraction challenges and problems.
  • Expert in Cadence Skill, Perl, Unix Shell and utilities
  • Excellent interpersonal, communication, and presentation skills

Backend Layout CAD Contractor

Looking for a qualified individual who can provide user support for Analog/Mixed Signal Backend Layout tool flows focused on advanced nodes. This individual will be hands-on, helping designers with their day-to-day issues, and in addition, interacting with EDA vendors, PDK developers, and process technology teams to provide timely solutions to improve productivity.

The candidate’s main responsibilities will also include CAD tool evaluations (debugging and proper characterization of layout related issues), automating testcase generation, timely and efficient testing of the design flow (tools, flow, OS, PDK) in addition to documentation and  continuous improvement of the regression flow methodology.

B.S. in Electrical Engineering or Computer Science + 3  years of Backend Layout EDA support experience

Additional requirements include:

  • Expertise in the following CAD Tools: IC and IC12/18 Cadence Virtuoso, Mentor Graphics Calibre,  SkillCAD
  • Solid background in programming skills, circuit design, and device physics knowledge to help solve layout challenges and problems
  • Experience in all phases of CAD tools from evaluation, QA, release, and user support to documentation
  • Expert in Cadence Skill, Perl, Unix Shell and utilities
  • Excellent interpersonal, communication, and presentation skills

Experience: 4-9 Yrs

Location: Hyderabad

Location: Bangalore

Experience: 6+Yrs

  • Experience in functional, performance testing in Linux
  • Basic programming skills in C, Python, bash.
  • Understanding of executing test cases in multi-core multi-node systems
  • Familiarity with Linux NUMA concepts
  • Familiarity with Linux based debugging tools, and system commands
  • Experience in automation with python/bash etc.
  • Graduate degree in Computer Science or related fields
  • Ability to quickly learn new skills and drive completion of business goals

Bonus skills:

  • Cluster management tools, CPU profiling tools, numa_ctl, mpirun
  • Understanding of openMP, MPI concepts
  • Any experience in bringing up full stack (BIOS, OS, Drivers) on any modern hardware.
  • Excellent verbal/written communication and evangelizing skills with an entrepreneurial spirit to drive results is a plus

Experience: 2-4 Yrs

Location: Malaysia

Location: Malaysia

Experience: 3-5 Yrs

Location: Malaysia

Experience: 3-5 Yrs

Location: Malaysia

Experience: 3-5 Yrs

Location: Bangalore

Minimum 2 years experience with x86 assembly, C++/C, Perl and at Ieast one scripting Ianguage on IInux and/or Windows – Minimum 2 years experience with CPU microarchitecture and Intel system architecture – Minimum 2 year experience in static and dynamic workload, benchmark, OS, driver, and system analysis, focusing on performance. Preferred Qualifications – 2+ years experience design and/or – Validation experience – 2+ years experience power consumption evaluation and – Validation methods – 2+ years experience performance evaluation and – Validation methods HS diploma or GED equivalent required for US candidates.

1. Knowledge of Android and chromebook performance benchmarks – how to run and analyse the results,
2. Able to work on linux hosts.
3. Knowledgeable with the Android SW stack.
4. Experience on performance regression analysis

Location: Bangalore

Experience: 6+Yrs

Description Job Description: This position is mostly BIOS and Firmware development in C for Server BIOS Firmware with minimum 6 years of experience in BIOS/UEFI development.

In this position, your responsibilities will include, but may not be limited to:

  • Designing, developing/coding, and debugging BIOS\Firmware
  • Debugging software and system issues
  • Responding to customer and/or client requests or events as they occur
  • Developing solutions to problems utilizing formal education, judgment, and formal software process
  • Demonstrate strong problem-solving skills and communication skills
  • Work well in a team environment.

Qualifications Minimum Qualifications
Must have a bachelor’s or Master of Science degree in Computer Science, Computer Engineering, Electrical Engineering or Software Engineering

Preferred Qualifications

  • 3+ years of experience in development of Legacy BIOS such as Phoenix, AMI and/or experience with UEFI, EDK, Tiano cores
  • 2+ years of experience working with Intel CPUs, memory controllers, IO Hubs, and PC architecture
  •  2+ years of experience with industry specifications such as PCI, ACPI, DDR
  •  3+ years of experience in direct FW development, C programming in an embedded context with constrained resources
  • 2+ years of experience with Intel x86 Assembly Language
  • 2+ years of experience in PC assembly/building skills
  • 3+ years of experience with PC architecture.

Location: Bangalore

Experience: 5+Yrs

Knowledge about H.W and S.W inventory with minimum of 5-7 years of experience, understand Inbound/Outbound Materials Flow Knowledge about STPI / Bonded/Duty Paid and with fairly good communication skill to interact with the Logistics and other Teams in Intel and with external Vendors.

Education background of BSc /Diploma

Exp: (2-5Yrs)

Physical Design, Netlist-to-GDSII, PnR, Timing Closures, STA, PD, PV

Role: It is an individual contributor role , where you are expected to own the block, take the block from RTL to GDS.

FINFET experience is mandatory

Exp: 5-8Yrs

Experienced physical design engineer with at least 5+ years of hands on experience with Innovus and ICC2 tools. The job would need P&R, CTS, and STA expertise.

The job would require a solid understanding of STA concepts, signal integrity basics, and experience with PTSi, Timing flows/configs.

Exp:  8-12Yrs

PNR expert with 8+ years of hands-on experience with netlist-to-gdsii digital P&R flows and PTSi expertise

Hands-on experience with EDI/Innovus, ICC2 tools

Experience in writing Tcl, Perl scripts

Hands on experience with advanced clocking CCOPT, MSCTS, Spine based clocking, CG Cloning, CTS Specs,

Solid understanding of STA concepts, Signal integrity basics, Experience with PTSi, Timing flows/configs.

Experience in PNR implementation and delivering good size designs on technology nodes: 28nm and below

Exp: 2-5 Yrs

Design, insertion and verification of the DFT structures, ATPG Pattern generation, logic simulation,


  • Implementation of advanced DFT/DFD (design for test/design for debug) techniques for high performance, highly integrated SoCs.
  • Work with design teams to improve low coverage on designs to desired target.
  • DFT features ATPG -experience with Mentor tool, MBIST pattern generation and verification -timing and no-timing simulations, debug.

Exp: 5-10Yrs

  • Sound knowledge in DFT Architecture and hands on in Scan stitching, ATPG and Simulation
  • Prior experience in Synsopsys Tetramax and DC tools
  • Hands on in MBIST insertion and simutation
  • Experience in Mentor Tessent tool for BIST
  • Good Simulation debugging skills

Exp: 2-5 Yrs

Verification UVM, SV expertise

Should be experienced in IP level functionality verification, testbench component design, concepts of constrained-random verification, SV assertions and coverage closure

Should have excellent verbal/written communication skills

Exp: 5-8Yrs

  •  Experience in Testbench Developement using System Verilog and UVM methodology.
  • Good in testcases/sequences coding.
  • Good at code coverage and functional coverage
  • Good Working knowledge on Protocols (AXI, PCIE and AHB).
  • Good debugging skills.
  •  Strong in System Verilog, Verilog and UVM methodology.
  • Basic Knowledge in specman ‘e’ language and scripting.

Exp: 8-12Yrs

  • Experience in Testbench Developement using System Verilog and UVM methodology.
  • Good knowledge on ethernet MAC, PHY and WLAN protocols 802.11X.
  • Knowledge on Gate level simulations(GLS).
  • Working knowledge on SoC verification.
  • Good in testcases/sequences coding.
  • Good at code coverage and functional coverage.
  • Good Working knowledge on Protocols (AXI and AHB).
  • Strong debugging skills.
  • Strong in System Verilog, RAL,UVM methodology.

Exp: 2-5Yrs

At least 2years of validation experience.

Experience in ARM Based SoC and its peripherals.

Excellent C programming skills.

Excellent debugging skills.

Expertise in using Lab equipments like Digital/Mixed Signal Oscilloscope, Logic Analyzer, Chipscope, protocol analyzer, etc.

Exp: 5-8 Yrs

Post Silicon SoC Validation experience. Hands-on experience on ARM/Sub-system based SoC validation.

CPU architecture knowledge – like Architecture, Caches, MMU, LPM, Security, etc

Silicon Debug and bring-up experience

Experienced in debugging production failures. Working experience related to one or more of the following is required.

ARM Processors & Debug – V7/V8 architectures like ARM Cortex-M, ARM Cortex-A7, ARM Cortex A53/A57 Debug experience based on ETM, ETB, STM, STB.

High speed Memories like LPDDR3, PCDDR3 High Speed peripherals like USB 2.0/3.0, MMC, PCI, SATA Low Speed peripherals like SPI, UART, I2C

Multimedia: – Audio: SlimBus, I2S, PCM. – Graphics: GPU, Video Codecs.

Display: HDMI, DSI – Camera: CSI System level Performance & Power Optimization and measurements..

Exp: 4+Yrs
Work location: Bangalore

Job Description :

  • Proficiency in Perl scripting and Data handling
  • Working knowledge on SQL (SQLlite preferred)
  • Prior experience on Version Control System (Subversion preferred)
  • Exposure to OS Concepts – LINUX Administration and Debugging
  • Good knowledge on software life cycle management
  • Self-starter with strong debugging skills
  • Good team player with interpersonal skills

Education: B.E / B.Tech / MCA  in Computer Science or Information Technology

Experience: 2 – 4yrs

Work location: Bangalore

SOC Verification: (Hyderabad, )

Note: Selected candidate will work in Emulation Team, he/she must have some knowledge on Emulation.

Must have good knowledge on the verification flows

Excellent hands-on debug skills and problem solving attitude.

Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC

Experience of working on Functional Verification, SoC Verification, Emulation

Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language

OVM/UVM Methodology knowledge and experience

Must have good communication skills and the ability to work in a team environment.

Preferably having experience in architecture such as x86 or ARM domain based SOCs

Experience in SOC emulation & corresponding methodologies is added advantage

Tools: Xilinx Tools, Mentor Veloce Quattro


SOC Emulation: (Hyderabad)

3-4 yrs experience on SOC verification & emulation

  • SOC/IP emulation experience is much needed
  • Should have basics of emulator environment/ flows
  • SOC verification experience is added plus
  • Excellent hands-on debug skills and problem solving attitude
  • Protocol & Architectural knowledge on CPU, IO devices is beneficial
  • Individual contributor and team player with abilities to interact with cross teams
  • Tools: Xilinx Tools, Mentor Veloce Quattro


We are looking for a candidate with experience in OpenGL/OpenGLES libraries.

Exp: 3+Yrs

Work location: Bangalore

The GPU Systems Team at Qualcomm leads the efforts to develop end to end architectural solutions for next generation Adreno graphics processing units (GPU)s. The Performance and Power team develops the necessary models and tools required to analyze the power and performance of these next gen architectures at various stages of development. Within this team the ideal candidate will have the following responsibilities 1.Analyze Graphics Application Performance at System level 2.Characterize various relevant Graphics Workloads (Gaming and UX) 3.Correlate Performance Projections from Model with Design 4.Identify GPU HW/Driver/Compiler Performance Optimizations 5.Develop tools to help improve Performance Debug

Minimum Qualifications:

Graphics Programming a combination of the following Open GL ES, GLSL Programming, DirectX, Open CL, Vulkan Programming etc.

Preferred Qualifications:

Graphics Programming a combination of the following Open GL ES, GLSL Programming, DirectX, Open CL, Vulkan Programming etc.