Careers


A Space Between Spaces

InSemi is constantly on a look out of people who understand the potential of innovation and who can think in-between the physical and the digital spaces. If you are someone who has a passion for VLSI, Embedded design and electronics, we have all the space for you.

Do write to us with your resume using below form..
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Current Openings

Experience: 8+Yrs

Location: Bangalore

As a Staff Firmware Development Engineer, you will join a team of professionals in developing software and real-time firmware solutions for state-of-art System-on-Chip (SoC) storage devices with embedded MIPS processors. Reporting to the Manager of Firmware Development, your responsibilities will include, but are not limited to the following:

  • Participate as a member of the team in the technical analysis and integration of storage software involving SATA/SAS/NVMe RAID controller technologies
  • Program MIPS processors using C and assembly language to implement core software/firmware components as well as device drivers.
  • Work directly with customers in the development of their software solutions using Microsemi devices and software/firmware components
  • Work in collaboration with other Microsemi sites to design solutions and resolve customer issues
  • Participate in detailed design and code reviews of implementations by team
  • Sustain current product and guide next generation product to production.
  • Troubleshoot and resolve complex software problems in embedded real-time systems.
  • Analyze software performance (d-cache and i-cache hit/miss rates, cycle counts, etc.) of firmware.
  • Write comprehensive engineering documentation.
  • Present technical information to teams of engineers and technical marketing personnel.

Experience: 4-9 Yrs

Location: Hyderabad

Experience: 2-4 Yrs

Location: Malaysia

Location: Malaysia

Experience: 3-5 Yrs

Location: Malaysia

Experience: 3-5 Yrs

Exp: (2-5Yrs)

Physical Design, Netlist-to-GDSII, PnR, Timing Closures, STA, PD, PV

Role: It is an individual contributor role , where you are expected to own the block, take the block from RTL to GDS.

FINFET experience is mandatory

Exp: 5-8Yrs

Experienced physical design engineer with at least 5+ years of hands on experience with Innovus and ICC2 tools. The job would need P&R, CTS, and STA expertise.

The job would require a solid understanding of STA concepts, signal integrity basics, and experience with PTSi, Timing flows/configs.

Exp:  8-12Yrs

PNR expert with 8+ years of hands-on experience with netlist-to-gdsii digital P&R flows and PTSi expertise

Hands-on experience with EDI/Innovus, ICC2 tools

Experience in writing Tcl, Perl scripts

Hands on experience with advanced clocking CCOPT, MSCTS, Spine based clocking, CG Cloning, CTS Specs,

Solid understanding of STA concepts, Signal integrity basics, Experience with PTSi, Timing flows/configs.

Experience in PNR implementation and delivering good size designs on technology nodes: 28nm and below

Exp: 2-5 Yrs

Verification UVM, SV expertise

Should be experienced in IP level functionality verification, testbench component design, concepts of constrained-random verification, SV assertions and coverage closure

Should have excellent verbal/written communication skills

Exp: 5-8Yrs

  •  Experience in Testbench Developement using System Verilog and UVM methodology.
  • Good in testcases/sequences coding.
  • Good at code coverage and functional coverage
  • Good Working knowledge on Protocols (AXI, PCIE and AHB).
  • Good debugging skills.
  •  Strong in System Verilog, Verilog and UVM methodology.
  • Basic Knowledge in specman ‘e’ language and scripting.

Exp: 8-12Yrs

  • Experience in Testbench Developement using System Verilog and UVM methodology.
  • Good knowledge on ethernet MAC, PHY and WLAN protocols 802.11X.
  • Knowledge on Gate level simulations(GLS).
  • Working knowledge on SoC verification.
  • Good in testcases/sequences coding.
  • Good at code coverage and functional coverage.
  • Good Working knowledge on Protocols (AXI and AHB).
  • Strong debugging skills.
  • Strong in System Verilog, RAL,UVM methodology.

Exp: 2-5Yrs

At least 2years of validation experience.

Experience in ARM Based SoC and its peripherals.

Excellent C programming skills.

Excellent debugging skills.

Expertise in using Lab equipments like Digital/Mixed Signal Oscilloscope, Logic Analyzer, Chipscope, protocol analyzer, etc.

Exp: 5-8 Yrs

Post Silicon SoC Validation experience. Hands-on experience on ARM/Sub-system based SoC validation.

CPU architecture knowledge – like Architecture, Caches, MMU, LPM, Security, etc

Silicon Debug and bring-up experience

Experienced in debugging production failures. Working experience related to one or more of the following is required.

ARM Processors & Debug – V7/V8 architectures like ARM Cortex-M, ARM Cortex-A7, ARM Cortex A53/A57 Debug experience based on ETM, ETB, STM, STB.

High speed Memories like LPDDR3, PCDDR3 High Speed peripherals like USB 2.0/3.0, MMC, PCI, SATA Low Speed peripherals like SPI, UART, I2C

Multimedia: – Audio: SlimBus, I2S, PCM. – Graphics: GPU, Video Codecs.

Display: HDMI, DSI – Camera: CSI System level Performance & Power Optimization and measurements..

Exp: 4+Yrs
Work location: Bangalore

Key skills

  • At least 5 – 10 years of relevant hands – on technical experience in Linux  WLAN driver development
  • Strong C/C++ programming skills
  • Must have strong understanding of WLAN protocols.
  • Must have hands on experience working in networking components in the Linux Kernel.
  • Must be extremely familiar with mac80211 implementation on Linux OS
  • Experience working on Wlan mac/phy protocols is a plus
  • Experience working with low memory systems and RTOS is a plus

Exp: 4-6 Yrs

CI/CD experience in software development

Platforms: Cloud & on-premise environments

Automate deployment & Configuration Management experience

Essential:

  1. Language – Python, bash, Perl, C, C++
  2. Platforms – BareMetal, VM (VMware)
  3. OS – Ubuntu, RHEL, Suse, CentOS
  4. SCM – Git, SVN, Gerrit
  5. CICD – Jenkins, Confluence, Jira
  6. Cloud – None
  7. Containers – Docker
  8. Build – cMake, Makefile, Autotools
  9. Monitoring – Nagios
  • 8-10 years of experience in the industry with relevant experience in the area of SoC / Microprocessor / Microcontroller / Embedded Systems verification, validation and customer support
  • Exposure to validation of IP modules / SoC subsystems / Interfaces such as Reset / Clock / CAN / SPI / LIN / UART / on-chip debug IPs etc.
  • Experience with building Embedded Software Applications
  • Knowledge about communication protocols is a must.
  • Must have proven debug skills with exposure to different debug tools
  • Hands-on experience in C, assembly, Perl / Python / Shell scripting is a must
  • Working knowledge of UNIX, Windows and embedded operating system
  • Experience in silicon validation using functional and requirement based validation methodologies
  • Familiarity with Pre-Si verification methodology, Post-Si validation concepts, test plans, post-Si validation environment, validation test case writing & debug with the required instruments, tools and environment
  • Working knowledge on emulation / simulation / Perspec would be an added advantage
  • Experience in using lab equipment’s such as Oscilloscopes, Protocol Analysers/Exercisers, Mid-bus Probes, Logic Analysers, JTAG based debuggers such as PLS, Lauterbach etc.
  • Candidates must have strong written and verbal communication skills
  • Good team player experienced in working with cross-site and cross-functional teams

Technical abilities demonstrated  through Ideas conceived & deployed

5 – 8  years of experience in the areas of analog and IO circuit design , with good experience in designing LVDS TX/RX interface.

Desired Skills :

  • Strong hands on experience in differential amplifier design, current mirror design, Impedance matching of transmission line, Feedback network analysis.
  • Solid hands on experience working with Cadence Virtuoso circuit design suite (ADE-XL)
  • Good understanding of the IEEE LVDS specification.
  • Good technical knowledge of power-performance trade-offs.
  • Strong understanding of the impact of device parameter variation on design performance.
  • Independent ownership of circuit blocks.
  • Clear communication and diligent documentation of the work.
  • Basic understanding of ESD & LU concepts.
  • Good team player in a multi-site work environment

Prior experience in redhawk and or voltus tool for IR analysis

Decent coding skills – perl/tcl

Some PD experience can be a bonus but not essential

Location: Bangalore

Experience: 4+ Years of relevant experience

  • Scan Insertion and scan DRC fixing for stitching using Design Compiler.
  • ATPG expertise using Tessent.
  • Scripting with perl / Tcl.
  • Awareness of scan Flows .
  • Mbist insertion using Tessent Mbist Shell skill set will help.

Location: Bangalore

Required Qualifications :

  • Bachelor’s Degree in Computer Science, Software Engineering, MIS, CIS, Engineering or relevant field
  • Minimum of 5 years applications/systems management or software development
  • 2-3+ years experience software development experience with Java, J2EE, Servlets, JSP, JDBC, SQL and DB2
  • Web development experience (AJAX, HTML CSS, PHP, javascript, and jQuery
  • Experience with Linux running JBOSS, web server and HTTP (programming and admin)
  • Linux skills with a good working knowledge of command line operations, shell scripts, crons and performance monitoring
  • Basic Semiconductor knowledge
  • CVS, GIT code repository knowledge
  • Fluency in English, both written and verbal
  • 24×7 support availability

Location: Bangalore

Required Qualifications :

  • Bachelor’s Degree with 2+ years of experience
  • Fluency in English Language – written & verbal – German is a plus.
  • User knowledge of UNIX, design software like Cadence K2 viewer, Mentor Calibre
  • Experiences in layout verification methodologies (SVRF)
  • Scripting and debugging skills
  • Basic Fundamental knowledge of Optical Lithography or Metrology
  • Travel 10% or Less
  • 4 to 8 years of experience of SoC.
  • Candidate should be good in Integration of SOC
  • Should be awrae of soC flow like  Spglass-Lint/Synthesis (DC)/CDC
  • Should be aware of scripting language .

BIOS Automation Testing – 8-10 years

Exp  on Jenkins ,Python

Hardware knowledge is good

CI frameworks and done patching works ,

Very strong in automation testing

Detailed JD below:

  • Develop, validate, release and maintain UEFI networking tool
  • Keep track of bugs reported and plan bug fix releases
  • Interact & support internal team requirements + customer requirements
  • Provide documentation support for tool – Internal design documents, external customer user guide
  • UEFI application developer with strong UEFI stack, SNP driver, networking knowledge
  • BIOS knowledge, experience is a plus

4-6 years experience

  • A minimum of 4-5 years of experience in Device Driver software testing which includes a good know how of standard software development Life Cycle.
  • Experience in AUTOSAR MCAL and exposure to ISO26262.
  • Embedded system software development or Validation using C, assembly languages.
  • Experience in the usage of LabView, NI, FPGA, oscilloscopes, logic analysers, power benches etc.
  • Experience in embedded system development tools such as compilers, debuggers (PLS, Lauterbach), static analysers etc.
  • Working experience in scripting languages such as Perl, python etc.
  • Experience in the development/maintenance of the test automation and continuous integration frameworks
  • Good knowledge of computer architecture (16/32bit), real-time systems
  • Working experience on multicore platforms
  • Ability and willingness to work with multi-disciplinary teams.
  • Ability to perform tasks independently.

Mandatory Skills:

  • Engineer with 8-10 years of experience in Windows driver framework. Strong C/C++ development skills with a good understanding of object-oriented design
  • Through debugging skills, using debug tools like WinDbg, BSOD analysis
  • Thorough understanding of OS internals, knowledge of system architecture like x86/ARM, and system buses like PCIE/SATA/USB/I2C/SPI, I/O Subsystems
  • Strong background in embedded systems development
  • Experience with low-level hardware device programming
  • Experience with Multi media/Graphics
  • Experience with silicon bring-up

Good to have:

  • Understanding of different Windows OS versions
  • Strong written and verbal communication skills
  • Self-motivated, should be able to take lead in mastering new technologies
  • Work in both an individual and team member environment
  • Experience in Linux development

Candidates shall have experience in Mother board design   X86 architecture (Latest experience must be on mother board)

High speed interfaces experience is must GEN3 PCIe,USB3.0 SATA, Gigabit Ethernet

Memory Interfaces DDR3/DDR4 and LPDDR

Board Bring-up, Functional Validation should be hands-on. Should be able to draft schematics independently. We are using Cadence Concept HDL  for schematics and Allegro 17.2 for Layout here.

Should be able to “drive discussions” with cross-functional teams like Layout, SI, Mechanical/Thermal, BIOS, Drivers, etc. and be hands-on in the usage of equipment (Scope, DMM, Function generator)

  • He needs a Linux admin guy with 3+yrs experience
  • Very good in scripting, Mandatory Shell & Perl
  • And while sharing Insemi format profile we need to keep company details also. Banu wants to know the company & project details of the candidates.
  • We need to do Internal Interviews with Arup as we are doing for HPC Linux admin req and then share the shortlisted profiles to client.

Qualifications / Experience:

  • BE/BS with 5 years experience.
  • Experience working with any one or more Java Benchmarks like Java Enterprise application, SPECJBB, SPECSERT, SPECPowerSSJ, benchmarks.
  • Experience working with one or more Microbenchmarks like Google Caliper, Apache JMeter etc.
  • Experience running performance benchmarking of complex Java enterprise workloads on single or multi-node clusters.
  • Excellent programming skills especially with scripting languages Python, Shell scripting, Perl on Linux.
  • Experience using any one or more JVM Performance tuning tools like PinPoint, Glowroot, Eclipse Memory Analyzer, Plumbr would be an added advantage.
  • Experience working with frameworks like YCSB, Cassandra, Hadoop, Spark would be an added advantage.
  • Ability to understand, C/C++/Java Programming will be an added advantage.
  • Good interpersonal and communication (written and oral) skills.

Need: Immediate to 30 days

Location: Bangalore

Exp: 3+

JD for Infra req (Exerciser):

  • B.E/B.Tech/M.E/M.Tech in Electrical/Electronic/Computer Engineering
  • Minimum 3+ years’ experience of industry experience with knowledge of Computer Architecture
  • Experience in any compute architecture such as x86 or ARM domain based SOCs/Cores.
  • Strong programming skills on C/C++ and Perl/Ruby/Shell programming skills
  • Stimulus/Generator/Random exerciser development for any complex products
  • Excellent hands-on debug skills
  • Must have good communication skills and the ability and desire to foster a team environment

Exp: 7-9 Yrs

  • Experience in Mobile Application Testing (Android and IOS App)
  • Experience in Home Automation mobile Application and worked with Home Appliances
  • Experience in Manual Testing and Automation Testing
  • Experience in Test Plan, Test case design, Test Execution
  • Bug reporting using any bug tools
  • Good communication skills and interaction with stakeholders

Skillset:

  • Good x86 architecture experience
  • Good knowledge of PCI, PCI Express, SPI Bus
  • Good understanding and experience in Firmware, Security Algorithms
  • High proficiency in C language and data structures
  • ARM architecture knowledge / experience is a plus
  • Hardware Bring up experience is a plus

R&R:

  • Coordinate with architects, Developers and peers to develop firmware security features
  • Work with Platform team to bring-up the BIOS and PSP firmware during bring-up
  • Work with Core teams for enablement of security features of SoC.
  • Design and drive platform Security firmware solutions. Perform timely releases for firmware.
  • Document newly developed features for Customers and IBVs. Participate in design reviews, code reviews for bug fixes and feature development.

Detailed JD below:

  • Develop, validate, release and maintain UEFI networking tool
  • Keep track of bugs reported and plan bug fix releases
  • Interact & support internal team requirements + customer requirements
  • Provide documentation support for tool – Internal design documents, external customer user guide
  • UEFI application developer with strong UEFI stack, SNP driver, networking knowledge
  • BIOS knowledge, experience is a plus
  • 4-6 years’ experience

Must:

Linux driver development

Linux Kernel – Network components experience

WLAN

C/C++

802.11/n/ac/b/g/ax

  • At least 5 – 10 years of relevant hands – on technical experience in Linux WLAN driver development
  • Strong C/C++ programming skills
  • Must have strong understanding of WLAN protocols.
  • Must have hands on experience working in networking components in the Linux Kernel.
  • Must be extremely familiar with mac80211 implementation on Linux OS
  • Experience working on Wlan mac/phy protocols is a plus
  • Experience working with low memory systems and RTOS is a plus
  • BIOS Automation Testing – 8-10 years
  • Exp  on Jenkins ,Python
  • Hardware knowledge is good
  • CI frameworks and done patching works
  • Very strong in automation testing

PnR expert  – 4-6 yrs experience

  • Experience with Cadence innovus tool
  • Good at floor-planning, macro placements
  • Power grid design
  • Good understanding of Clock tree design
  • Familiar with physical verification flows (DRC/LVS/ERC/ANT).
  • Understanding on running Power analysis.
  • Familiarity with TCL scripting.

STA expert  – 4-6 yrs experience

  • Experience with Cadence Tempus tool.
  • Should be able to run DMMMC scenarios.
  • generate eco scripts for Setup/Hold/DRV fixes
  • Able to understand the constraints.
  • Provide feedback on constraints to run the Designers to fix the violations

Ideal candidate will have:

  • A technology related Bachelor’s degree plus 5+ years or equivalent combination of training and experience
  • Experience in parameter extraction and knowledge on DDR, PCIe interface setup for high speed interface
  • Excellent debugging layout review skills related to signal integrity.
  • Extensive experience with engineering lab equipment, oscilloscopes, signal generators, VNAs
  • Must have excellent written and verbal communication skills for both internal and customer facing interaction
  • Hands on with Ansys, Sigrity and mentor tools

Please find the JD :

  • 2+ yrs of experience on using Emulator (Preferable : Synopsys Zebu emulator)
  • Should have good hands on C & HDL – Verilog language
  • Should be Familiar to SoC Architecture.
  • 6+ yrs in Project management
  • Program / Project Manager
  • Worked in Silicon industry
  • Experience in data center system design, software development, and validation
  • Experience in testing tools, methodologies, and defect tracking

3-5 Yrs

Experience in MCAL / LLD development / testing on any microcontroller but in Automotive domain

Preferable – experience on SoC drivers (Input/output/timers related)

Please find the below detailed JD below for Qualcomm.

The candidate should have 5-8 years of industry experience
Candidate in this role will need to have

  • Knowledge in of UNIX Operating systems like Red Hat Enterprise Linux / Ubuntu/SUSE and Solaris should be flexible and have cross platform working knowledge
  • In-depth familiarity and strong troubleshooting skills in Unix operation – Administration of physical and virtual infrastructure UNIX based hosts in complex heterogeneous environments.
  • Experience in Batch queuing technologies/LSF
  • Experience in Virtualization technologies (VMWare)
  • Knowledge of DNS, TCP/IP and other networking concepts
  • Experience with DBMS
  • Must be a self-starter, team player Excellent troubleshooting skills and customer support experience Customer Service oriented and thrive in a dynamic environment
  • Programming: Shell/Perl/Python scripting with automation experience
  • Preferred Exposure to Lab equipment like Lauterbach trace32

Exp: 5+Yrs

Exp in lower technology

Exp: 5+Yrs

Exp in 7nm or less than that

Exp: 5+Yrs

Exp: 7+Yrs

Experience – 2 to 5 yrs

Location – Bangalore

High-Speed Digital Hardware Characterization Engineer – The BDC Post Silicon Engineering group has an opening for a Digital Bench characterization Engineer.

As part of the Post Silicon Engineering group , you will be responsible for developing Test strategy & executing Bench characterization for leading edge LPDDR & PCDDR Subsystem components (DRAM, DRAM Controller, DRAM PHY, IOs, PLL/DLL, Clocking architecture, Delay circuits, Power Distribution Network) and High Speed IO interfaces ( PCIe, USB2/3, Display Port, HDMI, MIPI-CSI/DSI, UFS & PLL ).

You will drive first Silicon debug, qualify semiconductor fabrication process, , evaluate parametric performance of DDR & High Speed IO IPs and perform failure analysis to root-cause a design problem.

You with be working with IC design engineering, system engineering and Hardware applications engineering teams across the globe in a time critical environment.

  • MTech , B. Tech or Equivalent in Electronics or Electrical Engineering with 2-5 years of related work experience
  • Candidate must be familiar with Test and characterization of DDR and High-Speed IO interfaces with in-depth understanding of Mobile & PC DDR 2/3/4 protocol , timing diagrams, HSIO IPs PHY level understanding and Electrical parametric compliance specifications ( eye diagram, differential signaling, jitter analysis, Receiver-Jitter-Tolerance, signal integrity, transmission line considerations, de-embedding).
  • Hands-on experience using Bench instruments (oscilloscopes, J-BERT, network / spectrum analyzers, signal generators, logic analyzers) is a must. Required programming skills: C, C++, C-Sharp (or equivalent) and LabView.
  • Decent understanding of VLSI technologies, analog and digital integrated circuits, semiconductor physics.
  • Strong interpersonal, problem solving & debugging skills.
  • Need proven ability to work effectively in a fast-paced environment with strong verbal and written communication skills.

Exp: 5+Yrs

Detailed JD below:

  • Firmware/BIOS testing experience
  • Good knowledge of testing fundamentals
  • Good oral and written communication skills
  • Working knowledge of Linux and Windows OS
  • Excellent attitude towards work
  • Experience with any of scripting languages (e.g. Perl, python)

1-2 years experienced Candidates.

  • B.Tech in EEE/ECE.Well versed in digital signal processing concepts.
  • Well versed in C/C++ coding.
  • Should have at least 2 years prior experience in audio/speech signal processing/ codecs.
  • Experience in DSP firmware development is required.
  • Knowledge of audio pre/post-processing is recommended.

Exp: 4+ yrs

Positions: 1

  • Design and Validation of Power delivery solutions for Reference/Validation boards.
  • Design, development, testing and utilization of low voltage DC-DC regulators and power management circuits design for CPU/SOC based platforms and/or electrical components, mechanisms, materials, and/or circuitry, processes, for central processing units (CPUs) and/or peripheral equipment on a platform.
  • Design efforts includes understanding platform architecture and requirements to come up with design specification, schematics capture and integration, PCB layout review against design guides, component selection, release of Bill of Materials, support and release of relevant documents and test plans.
  • Ensures products conform to standards and specifications.
  • Develops plans and cost estimates and assesses projects to analyse risk.
  • Design efforts also involves working with BIOS/FW teams for receivables and deliverables for successful Power Delivery implementation.
  • Develops solutions to problems utilizing formal education and judgement.
  • Tool knowledge required for board design – Concept / Orcad for schematics capture, BOM tools and Cadence Allegro and Sigrity/Power DC for PCB layout reviews.

Lab work predominantly at Intel India Bangalore involving power-on, functional, electrical and stress validation, along with circuit/platform debug.

Tool knowledge required for board debug and validation – High speed oscilloscopes, electronic loads, current meters, DMM, logic analyzer, soldering station etc.

  • At least 6+ years of experience in Ruby on Rails(Ruby version 1.9+ and Rails version 5+)
  • In-depth knowledge of modern HTML/CSS, JavaScript
  • Be well versed in gems, Rails web services, messaging patterns, data engineering and OOPS background
  • Expertise implementing RESTful API’s in Ruby on Rails
  • Proficiency with writing the SQL queries
  • Hands-on experience in SQL/MYSQL database
  • Improving the quality of software without affecting features.
  • Basic knowledge of Continues Integration and Continues Development (GIT, Jenkins)
  • Experience designing with RSpec, TDD and CI
  • Good knowledge in Micro services

Nice to have:

  • Good Knowledge of anyone Front End framework(Angular/Vue/React)
  • Experience in any Cloud platforms (Openshift, Azure, etc..)
  • Knowledge on any Publish – Subscribe model (preferably KAFKA) is plus
  • Strong .NET and MVC (>=MVC4), C# (>4.0), Front end and JavaScript, Bootstrap skills is a must.
  • Experience in working with MSSQL / ORACLE / MYSQL database.
  • Experience is any reporting tools: SSRS, Crystal Reports, Tableau, etc.
  • Experience with the Agile development process.
  • Experience with WCF/ REST services. (nice to have)
  • Telerik (Nice to have).
  • Interaction with XML / JSON.
  • Experience with .NET core is a plus.

Responsibilities:

  • Individual contributor.
  • Should exhibit strong ownership and technical skills.
  • Working closely with teams in other regions to achieve the targets & collaborate.
  • Working on proof of concepts/demonstrators/reference solutions to support customers & build system knowledge.
  • Proven working experience in web programming
  • Top-notch programming skills and in-depth knowledge of modern HTML/CSS, JavaScript
  • Hands-on experience either in React JS or Vue JS is must
  • Experience in unit and e2e test automation (preferably jest & cypress)
  • Knowledge of web components and different component patterns
  • A solid understanding of how web applications work including security, session management, performance, and best development practices
  • Adequate knowledge of Object-Oriented Programming and web application development
  • Basic knowledge of Continues Integration and Continues Development (GIT, Jenkins)

Candidate must have a bachelor’s or master’s degree in Computer Science, Computer Engineering, Information Technology, or equivalent with 6-7 years of work experience in software development with at least 4-5 years of AEM development experience.

  • Proficiency in full-stack Java development.
  • Expertise in AEM 6.x.
  • Working experience with templates, components, bundles, Workflow, Forms Campaigns, Mobile pages, Newsletters, and Reports.
  • Hands-on experience in Apache Sling, AEM Dispatcher, JCR, Felix, J2EE, JSP, OSGi, JavaScript, JQuery, XML, JSON, XSLT, AJAX, CSS, and SQL, Junit, Sling Models, Editable Templates, HTL.
  • Experience with DITA, ideally the Adobe DITA solution.
  • Development experience in AngularJS/React.
  • Good problem-solving skills and ability to resolve issues with a quick turnaround.
  • Sound understanding and experience of the full software development life cycle.
  • Excellent verbal and written communication skills.
  • Experience building large scale web applications.
  • Strong understanding of Content Management Systems.
  • Experience with Agile development and DevOps practices.
  • Experience with GIT or other version control systems.
  • Proficiency in software engineering tools and CI/CD practices.

Job Description:

  • DFT flow expertise using Cadence and Mentor tools : 5+yrs experience with following details
  • Mentor Tessent Test compress : expert
  • Mentor LBIST Inserion and verification
  • Cadence NcSim – timing and zero delay mainly DFT verification
  • Cadence genus, LEC : Intermediate
  • Spyglass DFT – Nice to have
  • IJTAG – nice to have
  • 8-10 years of experience in SOC(system and chip) Project planning .
  • Proficient in MS project management, MS Excel project planner JIRA or any tracking system and possesses good analytical and communication skills.
  • Indicator Tracking / Checklist reviews , follow ups and reporting out to management .
  • Ability to work with multiple Stakeholders.
  • Attends regular scheduled meetings in order to help improvements to data management systems.
  • Proficiency in MS Access and other Office applications is a bonus.
  • Good to have VLSI Exp.

Experience: 3 – 5 years

Role: Software Developer

Mandatory Skills :

Strong communication and analytical skills

Programming language : Python, C#Good in algorithm , data structure , object oriented and test driven development experience

Good to have :

C++ basics and hands on experiences. Scripting language -RubyBasic knowledge of Linux

Mandatory Skills:

  • Engineer with 4-5 years of experience in embedded system (Linux device driver, Embedded systems, GFX and Multimedia)
  • Strong C/C++ skills with a good understanding of object-oriented design
  • Strong knowledge on OS concepts, Kernel understanding, Memory Managements.
  • Strong knowledge on Linux Operating system, logs(kern.log, dmesg,etc).
  • Knowledge on Multimedia(Audio, video codec formats) Basics and GFX.
  • Unit testing, white box testing of driver (Graphics, Multimedia, PCIE/SATA/USB/I2C/SPI, I/O Subsystems)
  • Debug analysis: Conducting Smoke, Integration, System, Functional, Regression
  • Supporting senior engineers with the debug data, traces, reproduction steps.
  • Debug tools (gdb, WinDbg, etc…)
  • System boot analysis.
  • Building release packages, Porting Linux, patching kernel, Validate bug fixes.

Good to have:

  • Experience in working on different Linux distributions like Ubuntu/RHEL/SUSE
  • Experience Windows device driver
  • Self-motivated, should be able to take lead in mastering new technologies
  • Work in both an individual and team member environment
  • Windows device driver validation
  • Test case development
  • OpenCL, OpenGL, DriectX, Vulkan testing

PREFERRED EXPERIENCE:

  • 6-8 years of experience in the x86 BIOS/UEFI development Experience with x86 CPU/APU architectures and associated compilation toolsExpert in C language; knowledge of x86 assembly.
  • Experience with platform bring-up.Familiar with at least one BIOS code base ( AMI, Insyde, or Phoenix BIOS)
  • Hands on experience with hardware debugging tools like AMD HDT, ITP, Arium, etc.
  • Able to read and interpret hardware schematics.
  • Knowledge of ACPI, USB, NVMe, SATA, PCIe and other PC industry standard
  • Knowledge of low-level protocols including I2c, I3c, SPI, eSPI, UART, etc. is expected
  • Hands on experience working with Reference Boards.
  • Strong communication skills

Exp:5-8 yrs

Skills required:

Knowledge of CAD tools and flows for Synthesis, place and route and signoff

  • Extensive knowledge in one of these areas

Basic perl/tcl scripting skills

Understanding of design flows and ability to learn new flows quickly.

Excellent Communication and Team work skills:

  • Team will have to interact and work jointly with local and overseas stakeholders and customers (local – BDC, remote – PNG, US, IDC).
  • These skills are essential for the success of the project.

Good Debug Skills

Technical & tools expertise:

  • Familiarity with industry standard EDA tools and design flow
  • Expertise in AS PER TOOL AREAS DEFINED BELOW
  • Closely work with project and program managers to align BLR activities with overall program of microcontroller development
  • Create project schedules, from bottoms up, for validation activities and drive alignment to overall program schedule
  • Familiarity with Pre-Si verification methodology, Post-Si validation concepts, Robustness Validation, test plans, post-Si validation environment, and test writing/debug
  • Must be familiar with Silicon validation using functional and requirement based validation methodologies to effectively design and deliver the quality product as per the automotive safety standards
  • Experience in using Microsoft Project, Microsoft Excel and other Project Management tools
  • Work closely with validation team members and Management to proactively come up with project risks and mitigation plan and effectively track & manage the risks to ensure delivery of high quality product, on-time & within budget
  • Work with verification teams across sites to collect requirement on validation projects to be executed in Bangalore
  • Collect requirement from team members, to perform their duties, e.g. trainings, Silicon, HW/SW tools, Debuggers, boards, etc., and work with local and cross-site management to provide solutions
  • Work with team members, Quality team and Management to ensure appropriate Validation Process is defined and followed to meet the Quality audit requirements
  • Good to have – ISO process knowledge (ISO9000, ISO26262 etc.,)
  • 4+ years of experience in relevant ASIC/SoC designs with an emphasis on CAD.
  • MS/PhD preferred, degree in technical field.
  • Multi-years working experience in at least one of the following areas:
  • SCAN/ATPG experience for SOC/ASIC design
  • Memory BIST experience for SOC/ASIC design
  • Boundary scan (JTAG) experience for SOC/ASIC design
  • SOC/ASIC design and ATE knowledge based silicon validation skill

Exp: 4-10Yrs

Job description:

  • Fully hands on with PNR tools like ICC /Encounter.
  • Hands on experience in defining ICC/Synthesis constraints that meets timing closure needs
  • In-depth knowledge of Signal and Power Floor plan with minimal EM/IR violations
  • In-depth expertise with all ICC options to handle de-ratings, Options to reduce cross talk
  • Hands on expertise with TCL/PERL to automate the end to end PNR flow.
  • Capability to handle a complex Netlist with multiple frequency domains and ICC timing closure.
  • Hands on experience in analyzing and correlating STA .vs. ICC timing reports.
  • Hands on Experience in DNE (final checks like LVS/DRC/DFM/Antenna etc.)and automation.
  • Familiarity with ECO flow, Implementing IR drop fixes.
  • Familiar with FinFet technology and design rules,
  • SPEF extraction, signal EM, power-EM, Noise analysis and fixes.
  • Knowledge of Synopsys tools ( Milkyway, Star-RC, Primetime,.. ) & exposure to cadence tools will be added advantage
  • Good scripting knowledge perl, TCL
  • Needs to be a very good team player.
  • 10+ years of exp
  • SV/UVM expertise
  • AXI experience
  • SOC Verif knowledge
  • Video encoder/decoder knowledge
  • Self-motivated

Exp: 3- 7 yrs’ experienced Memory Layout candidate

The candidate must have good communication skills and technical know how on lower technology nodes.

Must have BSEE in EE with 6-8 years of relevant experience.

Requirements :

  • Proficient on Synthesis, Static timing constraints , LEC/Formality
  • Strong knowledge of SOC design methodologies and flows
  • Good Knowledge of system-level architectures
  • Experience with Lint, CDC and STA
  • Work with RTL and DFT engineers, prepare SoC Top/Block level constraints
  • Work closely with SOC Team to achieve full chip timing, power, physical closure
  • Experience in timing & Functional ECO process
  • Create/ work on designs using Low Power Design Methodology.
  • Creates deliverables which do not require close review or supervision by a Senior Technical Lead.
  • Experience with Perforce or similar revision control environment
  • Excellent scripting skills in tcl/Perl/Shell.

Experience 3 – 5 years

Mandatory Skills :

  • Strong communication and analytical skills
  • Programming language : Python, C#
  • Good in algorithm , data structure , object oriented and test driven development experience

Good to have :

  • C++ basics and hands on experiences.
  • Scripting language -Ruby
  • Basic knowledge of Linux

Must:

C & Java (or) C++ & Java

Any SCM from the list

Build system : Linux (Yocto / Android)

Any Scripting language (2 is better)

Operation System: Linux, or QNX or Android (familiarity is POSIX standards) – If we can get QNX or Android is best

Debugging

CAN Protocol experience is MUST

White box testing (No need to search for this key word)

Must:

C & Java (or) C++ & Java

Any SCM from the list

Any Scripting language (2 is better)

Operation System: Linux, or QNX or Android (familiarity is POSIX standards) – If we can in QNX or Android is best

Debugging

Frameworks: Audio,  Display , Camera,  GNSS, BT and WIFI ( Minimum in 1 but expected is 2)

Familiarity with:  Physical Audio interfaces (I2S, TDM), I2C , SPI, SDIO  (At least 2)

Linux kernel concepts

CAN Protocol experience is MUST

  • 7+ years experience creating custom analog/mixed-signal layouts at chip, block, and device levels in deep sub-micron CMOS technologies – 28nm or below.
  • Expertise with Cadence Virtuoso XL schematic driven layout design flow, Virtuoso Floor Planning, Constraint Driven Layout, and extraction flows.
  • Expertise using Cadence verification suite (PVS-DRC, LVS, ERC); high proficiency with interpretation, debug, and understanding of results.
  • Strong experience with high performance analog layout techniques for device matching, common centroid layout, isolation, shielding, use of dummy devices, parasitic sensitivities, high speed routing, and also chip level electromigration, IR drop, self-heating, cross coupling capacitance and DFM practices.
  • Good understanding of package needs and constraints with respect to chip level.
  • Extensive layout lead experience with analog on-top and digital on-top flows, including defining, directing, and reviewing layout team’s work will be a plus
  • Proven capability at chip and block level in floor planning, power routing, ESD, physical design area estimates, effort/schedule estimations
  • Understanding of multiple voltage (HV) domains and layout techniques required.
  • Custom analog layout experience should include various analog IP blocks: PLLs, OSC, ADC, DAC, LDO Bandgap ref and other high speed connectivity ckts
  • Excellent communication skills and ability to work with cross-functional teams in a demanding team-oriented environment.
  • Scripting experience in PERL or SKILL CODE is considered a plus, but not required.

Detailed JD:

  • To work on any tasks related to changes, automation decided by Product Owner
  • Support and Solve incidents raised by our end-users
  • Prepare/Implementing Changes
  • Update Documentation/Procedures
  • Be a team-member in squads and to be pro-active/quality driven

Requirements:

  • Master or bachelor degree in IT or SW engineering
  • 4 years work experience
  • Extensive Experience with Linux Support/Administration ( RedHat & Ubuntu)
  • Good Knowledge on Supporting Windows based Environments ( Windows 10 , 2012 )
  • Working knowledge on Ansible, Experience writing Ansible playbooks is a plus!
  • Experienced with VMware administration / working in the Virtualized environment
  • Support experience in complex technical environments
  • Familiarity with software methods and tools
  • Good knowledge in Scripting (Bash/ Python)
  • Good to have the Agile / scrum methodology knowledge
  • Experience in working with international multi-site teams (team player!).
  • Effective communication skills and fluency in English are a must.
  • Candidate must have Experience between 5-10 Yrs of RTL front end verification
  • Experienced with SV & UVM methodology
  • Experienced working on C/ASM based SOC verification flow.
  • Functional and Code coverage analysis
  • Must Protocol knowledge : AHB, AXI, AXI Stream
  • Desirable to have experience on High speed peripherals like PCIe, USB3.0 etc
  • Gate Level Simulations will be an added advantage

Exp: 5+yrs

  • Linux / Windows
  • C and/or Assembly programming
  • Shell scripting / PowerShell scripting
  • Optimization
  • Multi core / Multi thread programming

Note: No Embedded profiles

Exp: 3+yrs

  • C & Python
  • Tools like perf
  • Multimedia (Codecs optimization)
  • Benchmarking and performance validation

Note: No Embedded profiles

Exp: 4-7 yrs

Positions:1

Job Description:

  • Hardware verification volume regression solution is a QT GUI framework that encapsulates several Validation solutions. This in turn is based on another legacy framework being based on a QT 4.8 version which further restricts its visual look and feel, and over all user experience.
  • We need to work on quality improvement , developing QT automated test environment to test the classes and functions and increase coverage matrix.
  • It needs a complete overhaul and removing legacy framework dependency, is one of the most critical and essential tasks.
  • This will also help reduce code complexity in Venus, transform it to Native QT and ease he debug process.
  • We also anticipate a considerable performance boost

Skills set :

  • QT expert, need to have native QT proven project– 3 – 7 years Exp.
  • Advantage to QT testing framework knowledge (QTestLib)
  • Ability to debug and develop big SW written in QT.
  • Advantage to someone who knows QT4 (not only QT5)
  • Need to have C++ recent experience
  • Good communications skills – fluent in English, can describe recent SW projects to details
  • Advantage: SQL knowledge

Exp: 5-8 yrs

Job Description:

  • Must have ARMv8/V9 CPU, Caches, MMUs, coherency, LPM features knowledge
  • Have worked with Lauterbach
  • Good coding skills , preferably C
  • Good analytical skills
  • A quick learner and willing to adapt to qualcomm fast-paced environment

Exp: 3-6 yrs

Job Description:

  • Node JS
  • Mongo DB (if no profiles go for NoSQL database)
  • EvenLoop Architecture
  • Microservice Architecture
  • REST API

Exp: 5+ yrs

Job Description:

  • Developer
  • Microservice Architecture
  • Javascript and Mean Stack
  • CI/CD (Jenkins)

Exp: 8-10 Yrs
Location:
BLR

Exp: 6 Yrs
Location:
BLR

Sl.No Details
1 Layer1 3-9 Yrs

L1 Control, L1 data

2 Layer2 3-9 yrs

MAC, RLC, PDCP

3 Layer3 3-9 Yrs

RRC

4 NAS (Non Access Stratum) 4-9 yrs

NAS

5 Layer4 2-9 yrs

Telephony, Positioning

 Required: 

  • B.E/B.Tech/B.S or M.E/MS in CS, EE or CE with 4+ years of software development experience 
  • Background in EDA tools preferred 
  • Demonstrated proficiency in scripting using Python and/or Perl 
  • Excellent problem-solving skills and willingness to think outside the box 
  • Experience with production software quality assurance practices, methodologies, and procedures 
  • Excellent communication skills and experience working with global teams 

Preferred:

  • Exposure to any of these areas: 
  • Experience in writing C++ code 
  • Exposure to FPGAs and FPGA software tool chain 
  • Good understanding of Perl/Python scripting 
  • Familiarity with Java/Javascripts/HTML
  • Candidate should have 7+ years of work experience in multiple software engineering projects
  • Work experience in Redis is must. 
  • Hands on experience with redis configuration/management.
  • Experience with setting up redis cluster (more than 20 nodes), optimization techniques on cluster.
  • Experience in Redis cluster failover management/configuration.
  • Experience/familiarity with respect to OOPS/Design techniques will be added advantage.
  • Initial contract period : 6 months (can be extended)

Experience: 4 – 8 yrs

Tech Stack/languages:

  • Front End: React.js and React Native (4 years, 3 recent mid-size projects)
  • Backend: Django (preferred), Node.js, MySQL, No-SQL DB (5 years, 3 recent mid-size projects)
  • AWS: VPC, IAM, EC2, S3, CloudFront, Beanstalk, Autoscaling, ELB, RDS, ElasticSearch, Lambda, SNS, LightSail, Batch, SageMaker (2 years, 2 recent mid-size projects)

Duties:

  • Develop visually appealing front end website architecture, including translating designer mock-ups and wireframes into front-end code
  • Design user interactions on web pages
  • Develop functional databases, applications, and servers to support websites on the back end
  • Ensure cross-platform optimization for mobile
  • Develop and design RESTful services and APIs
  • Ensure that non-functional requirements such as security, performance, maintainability, scalability, usability, and reliability are being considered when architecting solutions.

Traits:

  • Stay up to date on latest development trends in web applications and programming languages, and communicate the effectiveness to managers
  • Stay current and provide insight on cutting edge software approaches, architectures, and vendors
  • Keep job knowledge up-to-date by studying new development tools, programming techniques, and computing equipment; participating in educational opportunities; reading professional publications; maintaining personal and professional networks; participating in professional organizations.

Key Qualification

  • Must have BSEE in EE with 3-4 years of relevant experience:
     

Requirements :

  • Proficient on Synthesis, Static timing constraints , LEC/Formality 
  • Strong knowledge of SOC design methodologies and flows 
  • Good Knowledge of system-level architectures
  • Experience with Lint,  CDC and STA 
  • Work with RTL and DFT engineers, prepare SoC Top/Block level constraints 
  • Work closely with SOC Team to achieve full chip timing, power, physical closure 
  • Experience in timing & Functional ECO process 
  • Create/ work on designs using Low Power Design Methodology. 
  • Creates deliverables which do not require close review or supervision by a Senior Technical Lead. 
  • Experience with Perforce or similar revision control environment 
  • Excellent scripting skills in tcl/Perl/Shell. 
  • 10-12 years of industry experience 
  • Relevant experience in the area of embedded multicore application and device driver development. 
  • SoC / Microprocessor / Microcontroller verification, validation and customer support
  • Good programming experience in C, C++, assembly, Python / Shell scripting is a must
  • Working knowledge of UNIX, Windows and embedded operating system / RTOS
  • Strong in programming & OS concepts with a good understanding of embedded applications
  • Experience in developing new methodologies
  • Working knowledge on emulation / simulation would be an added advantage
  • Prior experience in matlab or similar platform would be an added advantage
  • Experience in using lab equipment such as Oscilloscopes, Power benches, Mid-bus Probes, Logic Analysers, debuggers such as PLS, Lauterbach etc. is desirable
  • Candidates must have strong written and verbal communication skills
  • Good team player experienced in working with cross-site and cross-functional teams
  • Technical abilities demonstrated  through Ideas conceived & deployed 
  • Exposure to automotive hardware/software development and validation is an added advantage
  • Any prior knowledge on HIL platform like dSPACE, SpeedGoat would be an added advantage

Exp: 5+Yrs

Location: HYD

  • Ensuring the various phases of specifications for applications embedding security, cryptography, security standards in the embedded and IoT solutions.
  • C and C++ programming and testing.
  • Integration and validation on target embedded microprocessor. (knowledge of ARC processors is preferable) 
  • Developing non-regression tests along with benchmarking tests.
  • Bringing innovative ideas to improve our products, the quality of deliveries and development processes.
  • Delivery of customers projects (consulting and training).

Exp: 5+Yrs

Location: HYD

  • Embedded software development engineer with 5 years minimum experience in an equivalent position. 
  • First experience in the field of Security protocols, Security practices, Key management, Signing and certification of communication protocols etc.
  • Experience in developing embedded library development.
  • Experience in creating/handling/manipulating Makefiles and build scripts for embedded firmware stack.
  • Bachelor’s degree (or higher) in Computer Science/ Electronics.
  • Proficiency in C/C++ language and assembly skills.
  • Knowledge of ARM/ARC processors, development for security and safety.
  • Proficiency in English.
  • Knowledge of embedded security practices in code.
  • Knowledge of embedded security in IoT and industry trends.
  • Knowledge of cryptography.
  • Excellent communication skills.
  • Ability to work in a team.
  • Outstanding analytical and problem-solving skills.
  • NAND/Storage domain knowledge is advantage.
  • Protocols – eMMC, UFS and NVMe 

Exp: 3+Yrs

Location: HYD

  • Ensuring the various phases of specifications for applications embedding security, cryptography, security standards in the embedded and IoT solutions.
  • C and C++ programming and testing.
  • Integration and validation on target embedded microprocessor. (knowledge of ARC processors is preferable)
  • Developing non-regression tests along with benchmarking tests.
  • Bringing innovative ideas to improve our products, the quality of deliveries and development processes.
  • Delivery of customers projects (consulting and training).

Exp: 3+Yrs

7nm is mandatory

Exp: 5+Yrs

IO/MXS circuit design profile

Work as part of IO and Mixed Signal Library Development team in Central Engineering. Primary responsibilities include:

  • Design and verification of IO interfaces such as LVCMOS,  I2C, GMII, LVDS, DDR/LPDDR HCSL and mixed signal blocks such as POR, process monitors, crystal oscillators etc.
  • Interface with layout engineers and oversee physical design and verification.
  • Develop functional models and perform timing characterization of these cells.
  • Create IO segments and necessary infrastructure to support silicon validation of these blocks on test chips.
  • Work with test engineers to support silicon validation either on ATE or on the bench.
  • Develop accurate documentation in the form of datasheets, application notes and integration guides.

Skills and Qualifications Required:

  • Educational requirements: MSEE with hands-on experience in independently designing IO and mixed signal/analog circuit design especially in newer CMOS technologies such as 16nm or 7nm.
  • Must have experience with Cadence Virtuoso Schematic Capture and ADE along with an excellent knowledge of spice based simulators such as Spectre and/or Hspice
  • Strong written and oral communication skills in English to be able to work effectively across geographies
  • Require proficiency in automation using shell scripting or any other languages such as SED, AWK, TCL or PERL
  • Working knowledge of LVS, DRC along with EM/ESD verification tools such as Totem/Pathfinder/PERC

Engineer with 4-6 yrs experience on C/C++ programming and debugging.

  • Hands on programming experience on C/C++
  • Hands on experience on Python scripting.
  • Ability to debug application issues on Linux environment.
  • Responsible for debugging and fixing issues in the application. Unit test features that are part of the SW application.
  • Capable of working independently.
  • Good knowledge on Jenkins , GIT and JIRA.

Teamcenter

Teamcenter Rich Client using Java

Server side customization using ITK (Integration ToolKit)

Teamcenter SOA and TCIC configuration & customization

CATIA/CAA Experience

Experience : 4-8 years

Programming Language:

  • Automation LabVIEW, TestStand – Must have
  • Embedded C – must-have
  • Understanding of SW Architectures – Must Have

Instrumentation Knowledge:

  • Lauterbach Debuggers (T32 knowledge)
  • General Lab Instruments (Oscilloscope, Power Supply, Multimeter, etc.)

Electrical char and functional for SPI, I2C, QSPI, UART, JTAG

Responsibilities:

  • He should implement optimized software by leveraging what the platform exposes.
  • He should be evaluate/test competitive products

Skills:

  • Expertise in C language, Python and shell script development including the tools used to edit, compile/assemble and debug code.
  • Experience in Linux kernel device drivers
  • Operating Systems (Linux kernel) internals, Systems management, Power Management
  • Experience in Developing software libraries and tools for the open source community.
  • Experience working with various communication and networking protocols
  • Should be well versed with using source control tools viz. GIT, Gerrit, JIRA
  • Setup development & test environment
  • Subject Matter Expertise in following areas are advantageous
    • X86 based server management
    • JSON, REST based services
    • BMC (Baseboard Manageement controller), OpenBMC, bmcweb, PowerAPI
    • RAS(Reliability Availability Serviceability), MCE(Machine check exceptions), MCA (Machine check architecture)

Education and Experience:

  • MS/M Tech/BE in Computer Engineering/Electronics/Electrical Engineering
  • Should have total experience of 6 – 8 years, with at least 4+ years of relevant experience
  • 6-10 years of experience in the industry, with relevant experience in the area of one or more high-speed communication interface (e.g., PCIE/ethernet/XSPI/MIPI ..) verification/validation for SoC / Microprocessor / Microcontroller and debug/root-cause of customer issues
  • Exposure to validation & characterization of interfaces and IPs such as PCIE/ethernet/XSPI/MIPI and its interactions with other interfaces/IPs, DMA, Interrupts, Reset, Clocking, Memory subsystem etc., is a must
  • Experience in silicon validation & measurements using functional and requirement based validation methodologies
  • Familiarity with Pre-Si verification methodology, Post-Si validation concepts, test plans, post-Si validation environment, validation test case writing & debug with the required instruments, tools and environment
  • Experience in embedded C, assembly, Python / Perl / Shell scripting is a must
  • Working knowledge of UNIX, Windows and embedded operating system
  • Working knowledge in emulation / simulation environments would be an added advantage
  • Experience in using lab equipments such as Oscilloscopes, Protocol Analyzers/Exercisers, Mid-bus Probes, Logic Analyzers, Debuggers such as PLS, Lauterbach etc. is mandatory
  • Candidates must have strong written and verbal communication skills

Exp: -8 yrs

Positions: 2

Job Overview:

  • Modem Hard Macro Synthesis and Implementation
  • Primary tasks include writing timing constraints, synthesis, formal verification, CLP, Primetime, PTPX, CECO
  • Lead, train and mentor team of junior CWF engineers to execute on a complex project for a large modem design in advanced process nodes
  • Work closely with DFT and PD leads worldwide to take a project from Post-RTL to Netlist release, and converge on area, timing, power
  • Use advanced features in synthesis such as MCMM, SAIF, multibit mapping, Fusion Compiler features etc.
  • Handle complex digital blocks with 1M-4M gates in advanced process nodes such as 3nm / 4nm / 5nm
  • Debug tool and flow issues independently

Minimum Qualifications – 5-8 years experience in Digital ASIC / Processor Design

  • Strong fundamentals in core areas: Microarchitecture, Computer Arithmetic, Circuit Design, Process Technology
  • Strong communication skills to work with design teams worldwide
  • Extensive experience in Synthesis (DC or FC), Formal Verification (LEC / Formality), Conformal Low Power, PTPX, Primetime, Conformal ECO
  • Extensive experience in UPF based power intent and synthesis

Education Requirements Required: Bachelor’s, Electrical Engineering

Preferred: Master’s, Electrical Engineering

Position: Senior Software Engineer

Experience: 3 – 7 years

Minimum Requirements / Desired Skills:

  • Graduate degree in Computer Science or related fields
  • Strong programming skills in C / C++
  • Strong programming in any scripting languages like Python, bash, etc.,
  • Strong debugging and problem-solving skills.
  • Experience using any of CPU profiling tools like gprof, and analyzing performance bottlenecks
  • Experience in Linux Kernel development along with decent understanding of kernel, BIOS hand-off
  • Ability to quickly learn new skills and drive completion of business goals

Experience : 4-8 years

Programming Language:

  • Automation LabVIEW, TestStand – Must have
  • Embedded C – must-have
  • Understanding of SW Architectures – Must Have

Instrumentation Knowledge

  • Lauterbach Debuggers (T32 knowledge)
  • General Lab Instruments (Oscilloscope, Power Supply, Multimeter, etc.)
  • Electrical char and functional for SPI, I2C, QSPI, UART, JTAG

JD is below:

We would like to hire .NET/C# developer with 3-8 years of experience, JD is here to get the skilled resource asap.

  • Work in Scrum environment and deliver value every sprint.
  • Understand customer/user requirements as described in user stories and derive appropriate actions.
  • Software design and development in .NET/C#, ASP.NET MVC, SQL Server following security principles.
  • Modular and scalable software architecture
  • Software test development.
  • Develop web services (REST/JSON, SOAP/XML) and Windows Services.
  • Present features short and crisp in user demo meetings for each application release.
  • Ensure results of development is under revision control and has passed reviews and tests
  • Ensure fulfilment of Definition-of-Done criteria in own area of responsibility for each deliverable, e.g. technical and user documentation, issue status and parameters, …
  • 8-10 years of experienced RTL Design engineer with good exposure in delivering the designs for IP or SoC with complete ownership covering MAS, RTL Coding in Verilog/SV, Design QC, Constraints, Power and Post-si debug.
  • Individuals should have very good understanding in handling multi clock domain designs with full ownership of CDC and timing constraints including the constraint qualification.
  • Should have worked on writing and qualifying the UPF for multi power domain design including the power estimations for RTL and Netlist.
  • Good working knowledge on SoC global design activities like Clock, Reset, Power management, IO, Security and Design for Debug.
  • Must have ability to work with all the cross functional teams like Architecture, DV, Timing, Physical design, Packaging, Validation, Emulation, FW/SW etc..
  • Additional knowledge on Multi CPU sub-systems, Ethernet Stack, SERDES designs, Networking and Packet Processing Ips will be added advantage.

Location: BLR

Exp: 3-5 yrs

Job Description:

  • Responsible for building and maintaining GLS testbench.
  • Responsible for generating constrained random tests for the DSP core and verify the Core netlists with and without timing.
  • Responsible for verifying Power aware correctness in the netlist through PAGLS.
  • Implement and deploy new verification methodologies, automation to continuously improve quality and efficiency

Exp: 3-5 yrs

Location: BLR

Worked on designing/ coding in software/EDA tools and flows

  • Hands on any Object oriented programming language and worked on Data Structures and Algorithms
  • Exposure to Unix/ Linux Platforms
  • Preferably having working knowledge in Perl/ Python
  • Understanding of UML modelling language preferred

Location: Hyderabad

Experience: 2+ Years

Job Description:

  • Will be responsible for verification and validation of Vivado tool flow.
  • Uses the product as a customer would to understand strengths and areas for improvement. Performs advanced interactive testing and can assist with defining quality metrics.
  • Provide input to product development teams.
  • Qualifications Required:
  • 0-2 yrs. with Masters / Bachelor or equivalent in the field of Electronics/Electrical Engineering from a reputed university.
  • PG-Diploma in VLSI from a reputed institute/university is a plus.

Technical Skills:

  • Proficient in RTL: VHDL/Verilog/System Verilog
  • Conceptual understanding of Digital Systems
  • Understanding of FPGA design flow and tools
  • FPGA Architecture knowledge
  • Good knowledge around all / any of following protocols / interfaces is highly preferred : SPI, IIC, PCIE, Ethernet, USB, HDMI, AXI, GTs, DDR4 (JEDEC)
  • Hands on debugging skills with on board as well as simulation environment
  • Expertise and hand-on with creating efficient automation and maintaining the high coverage regression suite to keep the quality intact.
  • Good Knowledge in Tcl, Python, Perl, Shell etc

Location: Hyderabad

  • B.Tech(ECE/CSC) or M.Tech (Embedded/Digital Signal Processing) or equivalent.
  • Well versed in digital signal processing concepts.
  • Well versed in C/C++ & Assembly language coding.
  • Should have at least 2 years prior experience in DSP firmware development.
  • Microcontroller programming & low-level debugging mandatory.
  • Excellent oral and written communication skills
  • Audio Codec programming (e.g., MP3 etc.) & FPGA/Pre-Silicon validation is a plus.
  • Windows Device Drivers experience is a plus.

Location: Hyderabad

  • B.Tech(ECE/CSC) or M.Tech (Embedded/Digital Signal Processing) or equivalent.
  • Well versed in digital signal processing concepts.
  • Well versed in C/C++ & Assembly language coding.
  • Should have at least 2 years prior experience in DSP firmware development.
  • Microcontroller programming & low-level debugging mandatory.
  • Excellent oral and written communication skills
  • Audio Codec programming (e.g., MP3 etc.) & FPGA/Pre-Silicon validation is a plus.
  • Windows Device Drivers experience is a plus.

Location: BLR

  • 7-8 years of experience
  • Expertise with C programming, Shell scripts
  • Experience with AMI Core BIOS and strong knowledge of industry standards like PLDM, IPMI, MCTP
  • Experience with baseboard management controller (BMC), onboard sensors, platform design
  • Good working knowledge of PCIe, USB, Serial (RS232), PXE
  • Experience in using PCIe Analyzer, Sniffer etc. for Platform SW/Diagnostics

Location: BLR

  • 5-6 years of experience
  • Experience with C and C++ language, object-oriented programming and with focus on secure programming
  • Strong Windows development skills, both service & application. Knowledge of Linux will be an advantage
  • Expertise in Windows system programming, network programming and database programming
  • Understanding of system hardware components and software ecosystem (Windows & Linux)
  • Should be versed with using enterprise tools viz. source control(git), bug tracking

Location: Bangalore

Experience:
4+ Years

JD:

  • Common skills: SOC integration experience with automation scripts and LINT, CDC, DFT checks with leading EDA vendor tool is a basic requirement
  • Power JD: Sound knowledge of low power design and power management concepts such as Power domains, Power state table, power switches, Clock Gating , Multi VT cells , Power Gating. Has experience of power architecture implementation, power estimation and power planning , knowledge on always on SoC domain is preferable. Good debugging skill
  • Bus JD: Sound knowledge of AMBA protocols like APB/AHB/AXI/ACE/ACE-Lite. Good understanding of interconnect design, SoC BUS architecture and NOC concept. Experience in SoC performance and latency tuning will be an add-on. Strong root causing and debugging skill.
  • Clock JD: Knowledge of Clocking IPs like PLLs, Oscillators and clock components like Clock Gating cells, Muxes and Dividers. Familiarity with low power concepts in Clock Architecture through Clock Gating, DVFS. Timing concepts and knowledge in CDC. Clock Jitter and fixes, Good debugging skills

Location: Bangalore

Experience: 3+ Years

Please find the JD for the requirement :

  • Must have the Zebu based emulation model build up and tool knowledge
  • Should have Basic understanding HDL language like Verilog or Systemverilog
  • Should be Basic knowledge of C programming language and anyone of scripting language like (shell, perl or python)

Exp: 3+Yrs