Physical Design & Signoff
Helping businesses achieve the best PPA goals in the least turnaround time
InSemi specializes in Physical Design services from RTL to GDSII leveraging Cadence & Synopsys EDA Flows.
Our strength lies in working on lower technology nodes like 3nm, 5nm, etc. The subject matter experts at InSemi are well versed with physical design flow and methodologies, ensuring projects achieve optimum power, performance, and area (PPA) goals.
The core objective of our team is to ensure customers with faster time to market by creating designs that swiftly skim through foundry-specific DRCs, LVS, and ERCs, avoiding multiple iterations.
Our Service Offerings
Synthesis
- Setting up the Synthesis Flow
- Developing Constraints
- Logic and Physical Aware Synthesis Using Industry Standard Tools
Physical Design (RTL - GDSII)
- RTL Synthesis (Logical & Physical aware)
- Design For test (Scan, MBIST, ATPG)
- Library Quality Checks, IP Validation
- Die Size Estimation (Bump and Ball requirement, MFU)
- IO Planning, Floor Planning, Partitioning
- Power Planning and Low Power Strategy
- Place & Route
- Clock Tree Synthesis
- Design for Manufacture (Metal Fill, Spare Cells, Decap Cells)
- Power Analysis (EM/IR)
- Physical Verification (DRC, LVS, ERC, ANTENNA, PERC, XOR)
- Low Power Checks (CLP) & Formality (LEC)
- Full Chip/Partition Timing Closure, MMMC Signoff
- ECO Iteration (Functional & Timing Fixes)
Static Timing Analysis (STA)
- Setting up the STA flow
- Develop Timing Constraints for Multiple Modes
- Timing Analysis for Multi Modes & Multi Corners
- Timing ECOs using TSO or DMSA
- SI Analysis
Logic Equivalence Check (LEC)
- Setting up the LEC flow for both Functional and CLP
- Block Level and Top Level LEC Runs
- Analysis & Debug skills for Complex Issues
Physical Design Flow
The team InSemi undergoes a rigorous research and focus the attention to all design aspects. Optimizing the design and other parameters, the turnkey product is delivered after an extensive examination.
